1. Field of the Invention
This invention relates generally to the field of semiconductor device manufacturing and, more particularly, to a method and apparatus for using feedback control of strip time to reduce post strip critical dimension variation in a transistor gate electrode.
2. Description of the Related Art
A continuing trend in semiconductor technology is to build integrated circuits with more and/or faster semiconductor devices. The drive toward this ultra large-scale integration (ULSI) has resulted in continued shrinking of device and circuit dimensions and features. In integrated circuits having field-effect transistors, for example, one very important process step is the formation of the gate electrode for each of the transistors, with particular emphasis being placed on the dimensions of the gate electrode. In many applications, the performance characteristics (e.g., switching speed) and size of the transistor are functions of the channel length of the device, which corresponds approximately to the width of the transistor""s gate electrode. Thus, for example, a narrower device with a smaller channel length tends to produce a higher performance transistor (e.g., faster) that is inherently smaller in size.
Typically, a gate electrode is formed by patterning a process layer comprised of the gate electrode material (e.g., polysilicon) using traditional photolithographic techniques. In accordance with conventional practices, an anti-reflective coating (ARC) is sometimes used to minimize notches caused by reflections during photolithographic techniques. Typically, an ARC layer is formed over a polysilicon layer. A photoresist layer is formed over the ARC layer. The ARC layer reduces the reflections and allows more effective patterning of the photoresist layer, which ultimately results in more effective formation of the gate electrodes from the polysilicon layer. Exemplary ARC layer materials are silicon oxynitride and silicon rich nitride.
Subsequent to the formation of the gate electrode, the ARC layer is removed using an etch process such as a hot hydrofluoric acid (HF) strip followed by a hot phosphoric acid (H3PO4) strip. The first hydrofluoric acid strip is relatively short and functions to remove a thin layer of silicon dioxide that grows on the surface of the ARC layer due to exposure to atmospheric oxygen. Such a silicon dioxide also forms on the exposed surface of the polysilicon gate electrode, but its removal is not the impetus for the hydrofluoric acid strip. The phosphoric acid strip, which is not particularly suited for removing silicon dioxide, removes the ARC layer covering the top surface of the gate electrode.
The phosphoric acid strip also slowly etches the polysilicon gate electrode, thus reducing its critical dimension. The strip rate of the phosphoric acid bath used to remove the ARC layer changes over its service life. Accordingly, the strip time used in the operating recipe of the strip tool includes a certain amount of overetch time to ensure that all of the ARC layer is removed even when the bath is at its most degraded level. The strip rate of the bath degrades based on the number of wafers etched due to the buildup of reaction products. The bath also degrades over time due to changes in the relative concentration of phosphoric acid oxidation states in the bath. Hence, wafers processed nearer the beginning of the bath service life will be stripped at a higher rate, resulting in a greater reduction in the critical dimension of the gate electrode. The variations in the strip rate of the bath translate to outgoing variations in the critical dimension of the gate electrode. Variations in the critical dimension of the gate electrode translate to variations in device speed, leakage, and other transistor performance parameters. Generally, increased variation reduces throughput, yield, and profitability.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
One aspect of the present invention is seen in a method for decreasing variations in gate electrode widths is provided. The method includes providing a wafer having a gate electrode formed thereon and an anti-reflective coating layer formed over at least a portion of the gate electrode. The gate electrode has a width. The width of the gate electrode is measured. A strip rate for a strip tool adapted to remove the anti-reflective coating is determined. The measured width of the gate electrode is compared to a target gate electrode critical dimension to determine an overetch time based on the strip rate. The operating recipe of the strip tool is modified based on the overetch time.
Another aspect of the present invention is seen in a processing line including a first metrology tool, a strip tool, and a process controller. The first metrology tool is adapted to measure the width of a gate electrode formed on a wafer. The gate electrode has an anti-reflective coating layer formed over at least a portion of the gate electrode. The strip tool is adapted to remove the anti-reflective coating. The process controller is adapted to determine a strip rate for the strip tool, compare the width of the gate electrode to a target gate electrode critical dimension to determine an overetch time based on the strip rate, and modify the operating recipe of the strip tool layer based on the overetch time.